`timescale 1ns/1ps

module  sync_r2w(      
                  //output
                  rp_s,

                 //input           
                  wr_clk,
                  wr_rst,
                  wr_clr,
                  rp_gray

                 );
  parameter aw=10;

output [aw:0]  rp_s;                   

input          wr_clk;
input          wr_rst;
input          wr_clr;
input  [aw:0]  rp_gray;

reg    [aw:0]  rp_p;  
reg    [aw:0]  rp_s;              

////////////////////////////////////////////////////////////////////
//
// Synchronization Logic
//
always @(posedge wr_clk  or negedge wr_rst)
if(!wr_rst)	
begin
	rp_p <= #1 {aw+1{1'b0}};
	rp_s <= #1 {aw+1{1'b0}};	
end
else if(wr_clr)	
begin
	rp_p <= #1 {aw+1{1'b0}};
	rp_s <= #1 {aw+1{1'b0}};	
end	
else
begin
	rp_p <= #1 rp_gray;
	rp_s <= #1 rp_p;	
end	                 


endmodule                 